In many conventional memory systems, a memory device such as synchronous DRAM (SDRAM) which is capable of inputting and outputting data in synchronization with an externally input high-speed clock has been used as processing speed has been increased. In particular, Double-Data-Rate (DDR) SDRAM can input and output data at both a rising edge and a falling edge of a clock, whereby the speed of input and output of data can be increased (see, for example, Non-Patent Document 1).
In a memory system employing a DDR SDRAM, data (DQ) is input and output in synchronization with both a rising edge and a falling edge of a data strobe (DQS) signal. However, the valid period of data decreases with an increase in the speed of clock frequency. For example, the valid period of data is 3 ns at 166 MHz. The valid period further decreases if the clock frequency is further increased. Moreover, the relationship between data and the strobe signal varies depending on various factors, such as a process characteristic, a change in temperature, a change in voltage and the like, and therefore, it is difficult to stably input and output data.
Therefore, a calibration process of adjusting access timing is performed so as to stably input and output data (see, for example, Patent Documents 1 and 2).
The calibration process includes two processes: a read calibration process involved in reading of data from a DDR SDRAM; and a write calibration process involved in writing of data to the DDR SDRAM.
The read calibration process includes:                a data write process of setting data in the DDR SDRAM;        a read timing range search process of obtaining a timing range within which read can be performed in a manner which allows read data to match written data, by changing a delay relationship between read data and a read strobe signal; and        an optimum read timing setting process of selecting and setting optimum timing from the read timing range (e.g., a center of a delay range within which read can be performed is selected).        
The write calibration process includes:                an optimum read timing setting process of setting optimum read timing selected in the read calibration process;        a write timing range search process of obtaining a timing range within which write can be performed in a manner which allows written data to match read data when data is written into and then read out from the DDR SRAM, by changing a delay relationship between write data and a write strobe signal; and        an optimum write timing setting process of selecting and setting optimum write timing from the write timing range (e.g., a center of a delay range within which write can be performed is selected).        
Thus, in order to read data from the DDR SDRAM with optimum timing, a read timing range is searched to select and set optimum read timing. In addition, in order to write data into the DDR SDRAM, a write timing range is searched to select and set optimum write timing.
The timing of data and a strobe signal can be typically changed by supplying information about a delay setting to a variable delay device with respect to a clock, the data and the strobe signal.
In the aforementioned conventional technique, the read calibration process is based on the assumption that timing with which data can be written is previously set into a memory cell of a memory device via data signal lines which are operated with a high-speed clock. In addition, in the DDR SDRAM, data is changed at half clock periods (half cycles) of the high-speed clock, and therefore, a period of time during which data is settled is short, and the timing of data and a strobe signal or the like needs to be set with precision and accuracy.
Recent DDR3-SDRAM has a read-only MPR (multi-purpose register) in which data (01010101) is previously set (see, for example, Non-Patent Document 2). By switching a data access path from a memory cell to the MPR using a selector, read calibration can be performed using the MPR in which data is previously set. However, as the previously set data is 01010101, data 0 and data 1 are read at a rise and a fall of a strobe signal, respectively. Therefore, calibration cannot be carried out with respect to both data 0 and data 1 at a rise and a fall of a strobe signal, and therefore, timing cannot be adjusted with accuracy, which is a problem.
Note that the present invention has storage means in a memory device and includes a process of setting data into the storage means within the memory device. A conventional example of this process is described in, for example, Patent Document 3. However, the subject matter of Patent Document 3 is directed to a technique of increasing the speed of setting of data into the storage means, and therefore, is not the calibration process technique pertaining to the present invention.